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1 idtcspu877 1.8v pll differential 1:10 sdram clock driver commercial temperature range y0 y0 fbout y1 y1 y5 y5 y4 y4 y3 y3 y2 y2 y8 y8 y6 y6 y7 y7 y9 y9 fbout fbin fbin pll clk clk power down and test mode logic ld av dd oe os ld or oe ld, os, or oe pll bypass 10k ? - 100k ? 2003 integrated device technology, inc. dsc-5962/34 c idtcspu877 commercial temperature range 1.8v phase locked loop differential 1:10 sdram clock driver august 2003 the idt logo is a registered trademark of integrated device technology, inc. functional block diagram note: the logic detect (ld) powers down the device when a logic low is applied to both clk and clk . description: the cspu877 is a pll based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(clk, clk ) to 10 differential output pairs (y [0:9] , y [0:9] ) and one differential pair of feedback clock output (fbout, fbout ). external feedback pins (fbin, fbin ) for synchronization of the outputs to the input reference is provided. oe, os, and a vdd control the power-down and test mode logic. when a vdd is grounded, the pll is turned off and bypassed for test mode purposes. when the differential clock inputs (clk, clk ) are both at logic low, this device will enter a low power-down mode. in this mode, the receivers are disabled, the pll is turned off, and the output clock drivers are disabled, resulting in a current consumption device of less than 500 a. the cspu877 requires no external components and has been optimised for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. the cspu877, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. the cspu877 is available in commercial temperature range (0 c to +70 c). see ordering information for details. features: ? 1 to 10 differential clock distribution ? optimized for clock distribution in ddr2 (double data rate) sdram applications ? operating frequency: 125mhz to 270mhz ? very low skew: 40ps ? very low jitter: 40ps ? 1.8v av dd and 1.8v v ddq ? cmos control signal input ? test mode enables buffers while disabling pll ? low current power-down mode ? tolerant of spread spectrum input clock ? available in 52-ball vfbga and 40-pin vfqfpn packages applications: ? meets or exceeds jedec standard 82-8 for registered ddr2 clock driver ? along with sstu32864/a, ddr2 register, provides complete solution for ddr2 dimms
2 commercial temperature range idtcspu877 1.8v pll differential 1:10 sdram clock driver pin configuration 52 ball vfbga package layout ab c e f g h j k d 6 y 7 fbin fbout y 6 fbout y 6 y 8 y 8 y 7 fbin 5 v ddq oe gnd y 5 y 9 gnd 4 y 9 y 5 v ddq 3 y 4 y 0 v ddq 2 y 0 y 4 gnd v ddq gnd 1 y 1 y 1 agnd av dd clk clk y 3 y 3 y 2 y 2 os gnd gnd gnd gnd nb nb nb nb nb nb v ddq v ddq v ddq gnd gnd nb nb gnd gnd v ddq v ddq v ddq vfbga top view 0.65mm top view a b c d e f g h j k a b c d e f g h j k 1 2 3 4 5 6 1 3 2 4 5 6
3 idtcspu877 1.8v pll differential 1:10 sdram clock driver commercial temperature range absolute maximum ratings (1,2) symbol rating max unit v ddq , av dd supply voltage range ?0.5 to +2.5 v v i (3) input voltage range ?0.5 to v ddq + 0.5 v v o (3) voltage range applied to any ?0.5 to v ddq + 0.5 v output in the high or low state i ik input clamp current 50 ma (v i <0) i ok output clamp current 50 ma (v o <0 or v o > v ddq ) i o continuous output current 50 ma (v o =0 to v ddq ) v ddq or gnd continuous current 100 ma tstg storage temperature range ? 65 to +150 c notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the maximum package power dissipation is calculated using a junction temperature of 150 c and a board trace length of 750 mils. 3. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. this value is limited to 2.5v max. recommended operating conditions symbol parameter min. typ. max. unit av dd (1) supply voltage v ddq v v ddq i/o supply voltage 1.7 1.8 1.9 v t a operating free-air temperature 0 ? +70 c capacitance (1) parameter description min. typ. max. unit c in input capacitance 2 ? 3 pf v i = v ddq or gnd c i ? delta input capacitance 0.25 pf clk, clk , fbin, fbin c l load capacitance ? 10 ? pf note: 1. unused inputs must be held high or low to prevent them from floating. v d d q y 5 y 6 y 6 y 0 y 5 y 0 y 1 y 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 v d d q 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 y 3 y 3 v d d q y 4 y 4 y 8 y 8 y 9 y 9 v d d q v ddq y 7 fbin fbin fbout 30 29 28 27 26 25 24 23 22 21 fbout oe os y 7 v ddq gnd v ddq y 2 y 2 agnd av dd clk clk v ddq 2 3 4 5 6 7 8 1 9 10 v ddq gnd vfqfpn top view note: 1. the pll is turned off and bypassed for test purposes when av dd is grounded. during this test mode, v ddq remains within the recommended operating conditions and no timing parameters are guaranteed. pin configuration
4 commercial temperature range idtcspu877 1.8v pll differential 1:10 sdram clock driver pin description (vfbga) pin name pin number description agnd g1 ground for 1.8v analog supply av dd h1 1.8v analog supply clk, clk e1, f1 differential clock input with a 10k ? to 100k ? pulldown resistor fbin, fbin e6, f6 feedback differential clock input fbout , fbout g6, h6 feedback differential clock output gnd b2 - b5, c2, c5, h2, h5, j2 - j5 ground v ddq d2 - d4, e2, e5, f2, g2 - g5 1.8v supply oe f5 output enable os d5 output select (tied to gnd or v ddq ) y [0:9] a3, a4, b1, b6, c1, c6, k1, k2, k5, k6 buffered output of input clock, clk y [0:9] a1, a2, a5, a6, d1, d6, j1, j6, k3, k4 buffered output of input clock, clk n b no ball pin description (vfqfpn) pin name pin number description agnd 7 ground for 1.8v analog supply av dd 8 1.8v analog supply clk, clk 4, 5 differential clock input with a 10k ? to 100k ? pulldown resistor fbin, fbin 26, 27 feedback differential clock input fbout , fbout 24, 25 feedback differential clock output gnd 10 ground v ddq 1, 6, 9, 15, 20, 23, 28, 31, 36 1.8v supply oe 22 output enable os 21 output select (tied to gnd or v ddq ) y [0:9] 3, 11, 14, 16, 19, 29, 33, 34, 38, 39 buffered output of input clock, clk y [0:9] 2, 12, 13, 17, 18, 30, 32, 35, 37, 40 buffered output of input clock, clk
5 idtcspu877 1.8v pll differential 1:10 sdram clock driver commercial temperature range notes: 1. h = high voltage level l = low voltage level x = don't care 2. l(z) means the outputs are disabled to a low state, meeting the i odl limit in dc electrical characteristics table. 3. the device will enter a low power-down mode when clk and clk are both at logic low. function table (1,2) inputs outputs av dd oe os clk clk y y fbout fbout pll gndhxlhlhlh off gndhxhlhlhl off gnd l h l h l(z) l(z) l h off l(z) l(z) gnd l l h l y 7 y 7 h l off active active 1.8v (nom) l h l h l(z) l(z) l h o n l(z) l(z) 1.8v (nom) l l h l y 7 y 7 hl on active active 1.8v (nom) h x l h l h l h o n 1.8v (nom) h x h l h l h l o n 1.8v (nom) x x l (3) l (3) l(z) l(z) l(z) l(z) off x x x h h reserved dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = 0c to +70c symbol parameter conditions min. typ. max. unit v ik input clamp voltage (all inputs) v ddq = 1.7v, i i = -18ma ?? ? 1.2 v v il (2) input low voltage (oe, os, clk, clk ) ?? 0.35v ddq v v ih (2) input high voltage (oe, os, clk, clk ) 0.65v ddq ?? v in (1) input signal voltage -0.3 ? v ddq + 0.3 v v id(dc) (2) dc input differential voltage 0.3 v ddq + 0.4 v v od (3) output differential voltage a vdd /v ddq = 1.7v 0.5 ?? v v oh output high voltage i oh = -100 a, v ddq = 1.7v to 1.9v v ddq - 0.2 ? v i oh = -9ma, v ddq = 1.7v 1.1 ? v ol output low voltage i ol = 100 a, v ddq = 1.7v to 1.9v 0.1 v i ol = 9ma, v ddq = 1.7v 0.6 i odl output disabled low current oe = l, v odl = 100mv, a vdd /v ddq = 1.7v 100 ?? a i in input current clk, clk a vdd /v ddq = max., v i = 0v to v ddq 250 a oe, os, fbin, fbin 10 i ddld static supply current (i ddq and i add )a vdd /v ddq = max., clk and clk = gnd 500 a i dd dynamic power supply current a vdd /v ddq = max., clk = 270mhz 300 ma (i ddq and i add ) (4,5) notes: 1. v in specifies the allowable dc excursion of each different output. 2. v id is the magnitude of the difference between the input level on clk and the input level on clk . the clk and clk v ih and v il limits are used to define the dc low and high levels for the power down mode. 3. v od is the magnitude of the difference between the true output level and the complementary level. 4. all outputs are left open (unconnected to pcb). 5. total i dd = i ddq + i add = f ck * c pd * v ddq , for cpd = (i ddq + i add ) / (f ck * v ddq ) where f ck is the input frequency, v ddq is the power supply, and c pd is the power dissipation capacitance.
6 commercial temperature range idtcspu877 1.8v pll differential 1:10 sdram clock driver timing requirements symbol parameter min. max. unit f clk operating clock frequency (1,2) 125 270 mhz application clock frequency (1,3) 160 270 mhz t dc input clock duty cycle 40 60 % t l stabilization time (4) ? 15 s notes: 1. the pll will track a spread spectrum clock input. 2. operating clock frequency is the range over which the pll will lock, but may not meet all timing specifications. to be used only for low speed system debug. 3. application clock frequency is the range over which timing specifications apply. 4. stabilization time is the time required for the integrated pll circuit to obtain phase lock of its feedback signal to its ref erence signal after power up. during normal operation, the stabilization time is also the time required for the pll circuit to obtain phase lock of its feedback signal to its reference s ignal when clk and clk go to a logic low state, enters the power-down mode, and later return to active operation. clk and clk may be left floating after they have been driven low for one complete clock cycle. ac electrical characteristics (1) symbol description test conditions min. typ. (2) max. unit t plh (2) low to high level propagation delay time a vdd = gnd, oe = h, os = l, tbd ns clk to any output t phl (2) high to low level propagation delay time a vdd = gnd, oe = h, os = l, tbd ns clk to any output t jit(cc+) jitter (cycle-to-cycle) 166/200/266mhz 0 40 ps t jit(cc-) 0 -40 t jit(per) (3) jitter (period) 166/200/266mhz -40 40 ps t jit(hper) (3) half-period jitter 166/200/266mhz -60 60 ps t slr(o) (1,4) output clock slew rate (single-ended) 166/200/266mhz (20% to 80%) 1.5 2.5 3 v/ns t slr(i) (1,4) output enable (oe) 0.5 ?? v/ns input clock slew rate 1 2.5 4 t ( ? ) (5) static phase offset 166/200/266mhz -50 50 ps t ( ? )dyn dynamic phase offset tbd tbd t sk(o) output skew 40 ps t en output enable to any y or y 8ns t dis output disable to any y or y 8ns v ox (6) ac differential output crosspoint voltage differential outputs terminated with 120 ? (v ddq /2) -0.1 (v ddq /2) +0.1 v v id(ac) ac differential input voltage 0.6 v ddq +0.4 v v ix ac differential input crosspoint voltage (v ddq /2) -0.15 (v ddq /2) +0.15 v the pll on the cspu877 will meet all the above test parameters while supporting ssc synthesizers with the following parameters: ssc modulation frequency 30 ? 33 khz ssc clock input frequency deviation 0 ? -0.5 % f 3db pll loop bandwidth 2 mhz notes: 1. there are two different terminations that are used with the above ac tests. the output load shown in figure 1 is used to mea sure the input and output differential pair cross-voltage only. the output load shown in figure 2 is used to measure all other tests, including input and output slew rates. for consis tency, use 50 ? equal length cables with sma connectors on the test board. 2. refers to transition of non-inverting output. 3. period jitter and half-period jitter specifications are seperate specifications that must be met independently of each other. 4. to eliminate the impact of input slew rates on static phase offset, the input slew rates of reference clock input (clk, clk ) and feedback clock input (fbin, fbin ) are recommended to be nearly equal. the 2.5v/ns slew rates are shown as a recommended target. compliance with these nominal values is not man datory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered ddr2 dimm application. 5. static phase offset does not include jitter. 6. v ox is specified at the ddr dram clock input or test load.
7 idtcspu877 1.8v pll differential 1:10 sdram clock driver commercial temperature range test circuit and switching waveforms figure 1: output load test circuit 1 figure 2: output load test circuit 2 v ddq cspu877 gnd r = 120 ? z = 60 ? z = 60 ? c = 10pf c = 10pf gnd gnd scope l = 2.97" l = 2.97" r = 1m ? c = 1pf 0v r = 1m ? c = 1pf 0v v ddq /2 v ddq /2 r = 10 ? z = 60 ? z = 60 ? c = 10pf c = 10pf z = 50 ? z = 50 ? r = 50 ? r = 50 ? 0v 0v r = 10 ? scope cspu877 v ddq /2 v ddq /2 l = 2.97" l = 2.97"
8 commercial temperature range idtcspu877 1.8v pll differential 1:10 sdram clock driver yx, fbout t jit(cc) t cycle n t cycle n+1 = yx, fbout t cycle n t cycle n+1 fbin clk t (?)n t (?)n + 1 t (?) = n n = n 1 t (?)n clk fbin (n is a large number of samples) cycle-to-cycle jitter static phase offset yx, fbout yx t sk(o) yx, fbout yx output skew test circuit and switching waveforms
9 idtcspu877 1.8v pll differential 1:10 sdram clock driver commercial temperature range yx, fbout yx, fbout t jit(per) = t cycle n 1 f o yx, fbout yx, fbout t cycle n 1 f o yx, fbout yx, fbout 1 f o t jit(hper) = t half period n 1 2*f o yx, fbout yx, fbout t half period n t half period n+1 period jitter half-period jitter test circuit and switching waveforms note: fo = average input frequency measured at clk / clk note: fo = average input frequency measured at clk / clk
10 commercial temperature range idtcspu877 1.8v pll differential 1:10 sdram clock driver test circuit and switching waveforms dynamic phase offset fbin clk t (?)dyn t (?) t (?)dyn ssc on ssc off clk fbin t (?)dyn t (?) t (?)dyn ssc on ssc off oe y/ y oe 50% v ddq t en 50% v ddq 50% v ddq t dis 50% v ddq y y y y time delay between output enable (oe) and clock output (y, y )
11 idtcspu877 1.8v pll differential 1:10 sdram clock driver commercial temperature range input and output slew rates clock inputs and outputs, oe 80% 20% v id , v od t r(i), t r(o) 80% 20% v 20% v 80% t slf(i/o) = t f(i/o) t f(i), t f(o) v 20% v 80% t slr(i/o) = t r(i/o) application information clock loading on the pll outputs (pf) clock structure # of sdram loads per clock min. max. #1 2 3 5 #2 4 6 10 test circuit and switching waveforms v ddq gnd via card via card bead 0603 4.7uf 1206 0.1uf 0603 2200pf 0603 av dd agnd v ddq gnd cspu877 1 ? 1 0.1uf 0603 10 recommended filtering for the analog and digital power supplies (av dd and v ddq ) notes: place all decoupling capacitors as close to the cspu877 pins as possible. use wide traces for a vdd and agnd. recommended bead: fair-rite p/n 2506036017y0 or equivalent (0.8 ? dc max., 600 ? at 100mhz).
12 commercial temperature range idtcspu877 1.8v pll differential 1:10 sdram clock driver application information clock structure 1 clock structure 2 cspu877 c = 10pf r = 120 ? fbin fbin c = 10pf r = 120 ? clk clk feedbac k path r = 120 ? z = 60 ? z = 60 ? 8 more sdram sdram ~2.5" ~0.3" ~0.6" (split to terminator) cspu877 c = 10pf r = 120 ? fbin fbin c = 10pf r = 120 ? clk clk feedback path r = 120 ? z = 60 ? z = 60 ? 8 more sdram sdram ~2.5" ~0.3" ~0.6" (split to terminator) sdram sdram stacked stacked
13 idtcspu877 1.8v pll differential 1:10 sdram clock driver commercial temperature range ordering information idtcspu xxxxx xx package device type 877 bv bvg nl very fine pitch ball grid array very fine pitch ball grid array. green thermally enhanced plastic very fine pitch quad flat pack no lead package 1.8v pll differential 1:10 sdram clock driver process blank 0c to +70c (commercial) x corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com

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